A well known conventional Field Effect Transistor (FET), whether metal semiconductor (MESFET), metal-oxide semiconductor (MOSFET), or heterostructure transistor (HEMT) is comprised of a source region or contact and a drain region or contact formed over a channel region. A gate region is formed over the channel between the source and drain. The FET is formed by well-known semiconductor processes including photolithography, diffusion and deposition of metals. An FET may have an n or p-type conductivity channel. The mechanism of operation divides all FETs into either depletion or enhancement mode operation.
A schematic of a prior art MESFET 10 operated in D-mode is shown in FIG. 1 to comprise a source region S and a drain region D with a gate region G laterally disposed between the source S and drain D and overlying a channel region generally shown as C. Superimposed on the MESFET is a curve P.sub.1 (shown in solid lines) of the E-field (E) in volts per centimeter (V/cm) plotted along the channel length L from O to L. When a single gate n-channel MESFET is operated in the depletion mode a negative or (positive) voltage V.sub.g. is applied to the gate G while the source S is grounded and the drain is under few volts of (positive) bias or negative depending upon the type of conductivity in the channel. Interaction of the gate and a drain potentials creates a nonuniform electric field. The signature of this nonuniformity is a shape of a depleted or enhanced region in various FETs as shown in the solid line profile P.sub.1 in the schematics of MESFET 10. In D-mode (depleted mode) MESFET operation of a single gate device, the weak electrical field at the source side results in slow moving electrons, a large opening of the channel C, and high parasitic capacitance C.sub.gs between the source S and gate G, which in turn impacts the performance of the MESFET. As a result, the velocity profile of the electrons in the channel of the single-gate FET is not efficient. As a matter of fact, the electrons reach their peak velocity, when they have traveled more than seventy percent of the channel C from the source S side to the drain D side of the channel. In E-mode (enhanced mode) transistors such as MISFETs, MOSFETs and alike the shape of the field P.sub.2 is shown in FIG. 2. The electron velocity profiles and C.sub.gs are opposite to what was shown in FIG. 1 and described above for D-mode devices.
The problem of non-uniformity of the electric field caused by the drain voltage, has been solved in the past by the concept of tailoring the field. The basic idea of the tailored field is to create a uniform electric field throughout the channel C, which would significantly counteract the effect of the drain voltage V.sub.d and increase the electron velocity at the source S end of the channel. (See "Observation of Negative Differential Resistance in GaAs Field Effect Transistors," P. Muzumdar et al J. Appl. Phys. 70 (2) Jul. 15, 1991).
The tailored field can be implemented in D-mode transistors by adding a number of gates G.sub.l. . . G.sub.n along the channel, between the source S and the drain D, while stepping up the bias voltage on the gates incrementally with the largest bias being applied to the gate G.sub.l, nearest the source S and the smallest applied to the gate nearest the drain D.
In E-mode transistors the electron carries high speed at the beginning of the channel C and loses it toward the drain D. Therefore, a small voltage should be applied to the first gate G.sub.l while increasing the bias at the next gate and so on. An optimum ratio of gate bias voltages applied to various gates can be determined based upon the design of a given transistor, its aspect ratio and regime of operation.